I am sure my keyboard controller works fine, as I tried it outindividually, shifter looks fine as well( I also tried this one on FPGA but without slowing the clock down, but nevertheless I was able to see the last scancode I entered), I haven't thought of any way/method to try out 7 segment controller, but that seems fine too. I am thinking that I have problems with clock, but seeing nothing on the display makes me think some part of the device is malfunctioning. I defined an 64bit std_logic_vector that can hold up to 8 scancodes, and then parsed the 4 MSBmost bytes of this vector, and directed them to seven segment controller, that muxes the inputs and decides which seven segment will be enabled. ![]() Now it is properly compiling and the RTL schematic seems true, but unfortunately I used a rather non-innovative way to shift the scancodes. ![]() The gure below shows a block diagram of a possible implementation of this controller. I can not resolve the problemĪfter deciding VHDL is having a hard time shifting indexes of arrays, I decided to change my shifter module. Our 4-digit seven-segment controller will take a clock and four characters (4-bit each) as inputs, and will write the seven-segment control signals as well as the four anode signals to display all four characters simultaneously. I am near to end in my project but stuck at some point.
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